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w3hg264m72eer-ad7 december 2005 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 2x64mx72 ddr2 sdram registered, w/pll, vlp mini-dimm description the w3hg264m72eer is a 2x64mx72 double data rate ddr2 sdram high density module. this memory module consists of eighteen 64mx8 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 244-pin dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option ? parity option features 244-pin, very low pro? le dual in-line memory module (vlp mini-dimm) fast data transfer rates: pc2-3200, pc2-4200, pc2-5300*, and pc2-6400* supports ecc error detection and correction v cc = v ccq = 1.8v 0.1v v ccspd = 1.7v to 3.6v differential data strobe (dqs, dqs#) option four-bit prefetch architecture programmable cas# latency (cl) posted cas# additive latency (al) on-die termination (odt) programmable burst lenghts: 4 or 8 serial presence detect (spd) with eeprom auto and self refresh capability (64ms: 8,192 cycle refresh) gold (au) edge contacts rohs compliant dual rank package option ? 244 pin mini-dimm ? pcb C 18.29mm (0.72") operating frequencies pc2-3200 pc2-4200 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 * contact factory for availability
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin names pin name function a0-13 address inputs ba0,ba1 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes dqs0#-dqs8# data strobes complement odt0, odt1 on-die termination control ck0,ck0# clock inputs cke0, cke1 clock enables cs0#, cs1# chip selects ras# row address strobe cas# column address strobe we# write enable reset# register reset input dm (0-8) data masks v ccspd spd power v cc v ccq i/o power (1.8v) a10/ap address input/auto precharge v ss ground par_in parity bit for the addess and control bus err_out parity error found on the address and control bus sa0-sa2 spd address sda spd data input/output scl clock input nc no connect v ref input/output reference pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 62 a4 123 v ss 184 v ccq 2v ss 63 v ccq 124 dq4 185 a3 3 dq0 64 a2 125 dq5 186 a1 4 dq1 65 v cc 126 v ss 187 v cc 5v ss 66 v ss 127 dm0 188 ck0 6dqs0#67 v ss 128 nc 189 ck0# 7 dqs0 68 nc/par_in 129 v ss 190 v cc 8v ss 69 v cc 130 dq6 191 a0 9 dq2 70 a10/ap 131 dq7 192 ba1 10 dq3 71 ba0 132 v ss 193 v cc 11 v ss 72 v cc 133 dq12 194 ras# 12 dq8 73 we# 134 dq13 195 v ccq 13 dq9 74 v ccq 135 v ss 196 cs0# 14 v ss 75 cas# 136 dm1 197 v ccq 15 dqs1# 76 v ccq 137 nc 198 odt0 16 dqs1 77 cs1# 138 v ss 199 a13 17 v ss 78 odt1 139 nc 200 v cc 18 reset# 79 v ccq 140 nc 201 nc 19 nc 80 nc 141 v ss 202 v ss 20 v ss 81 v ss 142 dq14 203 dq36 21 dq10 82 dq32 143 dq15 204 dq37 22 dq11 83 dq33 144 v ss 205 v ss 23 v ss 84 v ss 145 dq20 206 dm4 24 dq16 85 dqs4# 146 dq21 207 nc 25 dq17 86 dqs4 147 v ss 208 v ss 26 v ss 87 v ss 148 dm2 209 dq38 27 dqs2# 88 dq34 149 nc 210 dq39 28 dqs2 89 dq35 150 v ss 211 v ss 29 v ss 90 v ss 151 dq22 212 dq44 30 dq18 91 dq40 152 dq23 213 dq45 31 dq19 92 dq41 153 v ss 214 v ss 32 v ss 93 v ss 154 dq28 215 dm5 33 dq24 94 dqs5# 155 dq29 216 nc 34 dq25 95 dqs5 156 v ss 217 v ss 35 v ss 96 v ss 157 dm3 218 dq46 36 dqs3# 97 dq42 158 nc 219 dq47 37 dqs3 98 dq43 159 v ss 220 v ss 38 v ss 99 v ss 160 dq30 221 dq52 39 dq26 100 dq48 161 dq31 222 dq53 40 dq27 101 dq49 162 v ss 223 v ss 41 v ss 102 v ss 163 cb4 224 nc 42 cb0 103 sa2 164 cb5 225 nc 43 cb1 104 nc 165 v ss 226 v ss 44 v ss 105 v ss 166 dm8 227 dm6 45 dqs8# 106 dqs6# 167 nc 228 nc 46 dqs8 107 dqs6 168 v ss 229 v ss 47 v ss 108 v ss 169 cb6 230 dq54 48 cb2 109 dq50 170 cb7 231 dq55 49 cb3 110 dq51 171 v ss 232 v ss 50 v ss 111 v ss 172 nc 233 dq60 51 nc 112 dq56 173 v ccq 234 dq61 52 v ccq 113 dq57 174 cke1 235 v ss 53 cke0 114 v ss 175 v cc 236 dm7 54 v cc 115 dqs7# 176 nc 237 nc 55 nc 116 dqs7 177 nc 238 v ss 56 nc/err_ out 117 v ss 178 v ccq 239 dq62 57 v ccq 118 dq58 179 a12 240 dq63 58 a11 119 dq59 180 a9 241 v ss 59 a7 120 v ss 181 v cc 242 sda 60 v cc 121 sa0 182 a8 243 scl 61 a5 122 sa1 183 a6 244 v ccspd
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram rcs0# rcs1# rcke0 rcke1 rodt0 rodt1 dqs0 dqs0# dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dqs1# dm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs2 dqs2# dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs3 dqs3# dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dqs4# dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs5 dqs5# dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs6 dqs6# dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs7 dqs7# dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 dqs8# dm8 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s# cke odt dqs dqs# dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 r e g i s t e r s (x2) cs0# cs1# a0~a13 ba0~ba1 ras# cas# we # odt0 odt1 cke0 cke1 pck pck# rcs0# to s# ddr2 sdrams rcs1# to s# ddr2 sdrams ra0~ra13 ddr2 sdrams rba0~rba1 ddr2 sdrams rras# rcas# rwe# rodt0 ddr2 sdrams rodt1 ddr2 sdrams rcke0 ddr2 sdrams rcke1 ddr2 sdrams reset# a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ccspd v cc /v ccq v ref v ss serial pd ddr sdrams ddr sdrams ddr sdrams p l l oe ck0 ck0# reset# ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram ddr2 sdram register note: all resistor values are 22 ohms 5% unless otherwise speci? ed.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol min typical max unit notes supply voltage v cc 1 .7 1 .8 1 .9 v 1 i/o supply voltage v ccq 1 .7 1 .8 1 .9 v 4 v ccl supply voltage v ccl 1 .7 1 .8 1 .9 v 4 i/o reference voltage v ref 0.49 x v ccq 0.50 x v ccq 0.51 x v ccq v2 i/o termination voltage v tt v ref -0.04 v ref v ref + 0.04 v 3 notes: 1. v cc and v ccq must track each other. v ccq must be less than or equal to v cc . 2. v ref is expected to equal v ccq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not excedd 1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref (dc). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v ccq tracks with v cc ; v cc l track with v cc . absolute maximum dc ratings symbol parameter min max u nit v cc voltage on v cc pin relative to v ss -1.0 2.3 v v ccq voltage on v ccq pin relative to v ss -0.5 2.3 v v ccl voltage on v ccl pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c t case device operating temperature 0 85 c t opr operating temperature (ambient) 0 55 c i l input leakage current; any input 0v w3hg264m72eer-ad7 december 2005 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature t oper 0c to 85c c v notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. forthe measurement conditions, ple ase refer to jedec jesd51 .2 2. at 0 - 85c, operation temperature range, all dram speci? cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max unit input high (logic 1 ) voltage v ih (dc) v ref + 125 v ref + 300 mv input low (logic 0) voltage v il (dc) -300 v ref - 125 mv input ac logic level all voltages referenced to v ss parameter symbol min max unit ac input high (logic 1 ) voltage (ddr2-400/533) v ih (ac) v ref + 250 mv ac input high (logic 1) voltage (ddr2-667) v ih (ac) v ref + 200 mv ac input low (logic 0) voltage v il (ac) v ref - 250 mv
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 i cc specifications and conditions includes ddr2 sdram components only; t a = 0c, v cc = 1.9v symbol parameter condition 806 667 534 403 unit i cco* operating one bank active-precharge; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,525 1,615 1,795 ma i cc1* operating one bank active-read- precharge; i out = oma; bl = 4; cl = cl(i cc ); t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching; data pattern is sames as i cc4w . tbd 1,615 1,750 1,930 ma i cc2p** precharge power- down current; all banks idle; t ck = t ck(i cc ) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 490 490 490 ma i cc2q** precharge quite standby current; all banks idle; t ck = t ck(i cc ) ; cke is high; cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 1,030 1,120 1,300 ma i cc2n** precharge standby current; all banks idle; t ck = t ck(i cc ) ; cke is high; cs# is high; other control and address bus inputs are stable; data bus inputs are switching tbd 1,120 1,210 1,390 ma i cc3p** active power-down current; all banks open; t ck = t ck(i cc ) , cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 1,030 1,165 1,300 ma slow pdn exit mrs(12) = 1 tbd 895 985 1,075 ma i cc3n** active standby current; all banks open; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 1,210 1,390 1,570 ma i cc4w* operating burst write current; all banks open; continuous burst writes; bl = 4; cl = cl(i cc ); al = 0; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,840 2,155 2,470 ma i cc4r* operating burst read current; all banks open; continuous burst reads; tout = oma; bl = 4; cl = cl(i cc ); al = 0; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w . tbd 1,840 2,200 2,560 ma i cc5** burst auto refresh current; t ck = t ck(i cc ) ; refresh command at every t rc(i cc ) interval; cke is high; cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 2,515 2,695 2,875 ma i cc6** self refresh current; ck and ck# at ov; cke < 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal tbd 90 90 90 ma i cc7* operating bank interleave read curent; all bank interleaving reads; i out = oma; bl = 4; cl = cl(i cc ); al = t rcd(i cc ) - 1*t ck(i cc ) ; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t rrd = t rrd min(i cc ) = 1*t ck(i cc ) ; cke is high; cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching tbd 2,875 3,235 3,415 ma notes: i cc speci? cation is based on micron components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operating condition, and all other module ranks in i cc2p ( cke low) mode. ** value calculated re? ects all module ranks in this operating condition.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 667 534 403 parameter symbol min max min max min max min max unit notes clock clock cycle time cl = 6 t ck (6) tbd tbd ps 16, 24 cl = 5 t ck (5) tbd tbd 3,000 8,000 ps 16, 24 cl = 4 t ck (4) tbd tbd 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24 cl = 3 t ck (3) tbd tbd 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24 ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck 18 ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck 18 half clock period t hp tbd tbd min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps 19 data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac (max) t ac max t ac max ps 8, 9 data-out low-impedance window from ck/ck# t lz tbd tbd t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) ps 8, 10 dq and dm input setup time relative to dqs t dsa tbd tbd 100 100 100 ps 7, 15, 21 dq and dm input hold time relative to dqs t dha tbd tbd 175 225 275 ps 7, 15, 21 dq and dm input setup time relative to dqs t dsb tbd tbd 100 100 150 t ck 7, 15, 21 dq and dm input hold time relative to dqs t qhb tbd tbd 175 225 275 ps 7, 15, 21 dqdqs hold, dqs to ? rst dq to go nonvalid, per access relative to dqs t dipw tbd tbd 0.35 0.35 0.35 ps data hold skew factor t qhs tbd tbd 340 400 450 dqCdqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs 15, 17 data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq 15, 17 data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck risingC setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising C hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqsCdq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps 15, 17 dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck 35 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (continued) 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit notes data strobe dqs read preamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck 35 dqs write preamble setup time t wpres tbd tbd 0 0 0 ps 12, 13, 36 dqs write preamble t wpre tbd tbd 0.35 0.25 0.25 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck 11 write command to ? rst dqs latching transition t dqss tbd tbd wl- 0.25 wl- 0.25 wl- 0.25 t ck command and address address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t isa tbd tbd 400 500 600 ps 6, 21 address and control input hold time t iha tbd tbd 400 500 600 ps 6, 21 address and control input setup time t isb tbd tbd 200 250 350 ps 6, 21 address and control input hold time t ihb tbd tbd 275 375 475 ps 6, 21 cas# to cas# command delay t ccd tbd tbd 222t ck active to active (same bank) command t rc tbd tbd 55 55 55 ns 33 active bank a to active b bank command t rrd tbd tbd 7.5 7.5 7.5 ns 27 active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 ns 30 active to precharge command t ras tbd tbd 40 70,000 40 70,000 40 70,000 ns 20, 33 internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns 23, 27 write recovery time t wr tbd tbd 15 15 15 ns 27 auto precharge wirte recovery and precharge time t dal tbd tbd t wr +t rp t wr +t rp t wr +t rp ns 22 interval write to read command delay t wtr tbd tbd 10 7.5 10 ns 27 precharge command period t rp tbd tbd 15 15 15 ns 31 precharge all command period t rpa tbd tbd t rp +t ck t rp +t ck t rp +t ck ns 31 load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is +t ck+ t ih t is +t ck+ t ih t is +t ck+ t ih ns 28 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (continued) 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit notes self refresh refresh to active or refresh to refresh command interval t rfc tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns 14 average periodic refresh interval t refi tbd tbd 200 7.8 7.8 7.8 s 14 exit self refresh to non-read command t xsnr tbd tbd t rfc (min) +10 t rfc (min) +10 t rfc (min) +10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference t isxr tbd tbd t is t is t is ps 6, 29 odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac(min) t ac(max) +700 t ac(min) t ac(max) +1,000 t ac(min) t ac(max) +1,000 ps 25 odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 ps 26 odt turn-on (power-down mode) t aonpd tbd tbd t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ck odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7-al 6-al 6-al t ck exit precharge power-down to any non-read command. t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck 34 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs notes 1. all voltages referenced to v ss 2. tests for ac timing, i cc, and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: 4. ac timing and i cc tests may use a v il to v ih swing of up to 1.0v in the test environment parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew rates less than 1.0v/ns require the timing parameters to be derated as speci? ed. 5. the ac and dc input level speci? cations are as de? ned in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate is at 1.0v/ns. command/address input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated using t isb and the setup and hold time derating values table. t is timing (t isb) is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal. t ih timming (t ihb ) is referenced from v ih (ac) for a rising signal and v il (dc) for a falling signal. the timing table also lists the t isb and t ihb values for a 1.0v/ns slew rate; these are the base values. 7. data minimum input slew rate is at 1.0v/ns. data input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated if the timing is referenced from the logic trip points. t ds timing (t dsb ) is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal. t ih timing (t ihb ) is referenced from v ih (dc) for a risng signal and v il (dc) for a falling signal. the timing table lists the t ds b and t dh b values for a 1.0v/ns slew rate. if the dqs/dqs# differential strobe feature is not enabled, timing is no longer referenced to the crosspoint of dqs/dqs#. data timing is now referenced to v ref , provided the dqs slew rate is not less than 1.0v/ns. if the dqs slew rate is less than 1.0v/ns, then data timing is now referenced to v ih (ac) for a rising dqs and v il (dc) for a falling dqs. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (t hz ) or begins driving (t lz ). 9. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) t lz will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the dont care state after completion of the postamble is the dqs-driven signal should either be high, low or output (v out ) reference point 25? v tt = v cc q/2 high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transi- tions high (above v ih dc (min) then it must not transition low (below v ih (dc) prior to t dqsh (min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turn around. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8192 refresh commands must be issued every 64ms. 15. each half-byte lane has a corresponding dqs. 16. ck and ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). 17. the data valid window is derived by achieving other speci? cations - t hp . (t ck /2), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum speci? cation limits for t cl and t ch . for example, t cl and t ch are = 50 percent of the period, less the half period jitter [t jit (hp)] of the clock source, and less the half period jitter due to cross talk [t jit (cross talk)] into the clock traces. 19. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. 20. reads and writes with auto precharge are allowed to be issued before tras (min) is satis? ed since t ras lockout feature is supported in ddr2 sdram devices. 21. v il /v ih ddr2 overshoot/undershoot. refer to the 512mb ddr2 sdram data sheet for more detail. 22. t dal = (nwr) + (t rp /t ck ): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for 534 at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. 23. the minimum read to internal precharge time. this parameter is only applicable when t rtp /2*t ck ) > 1. if t rtp /2*t ck ) 1, then equation al + bl/2 applies. notwithstanding, t ras (min) has to be satis? ed as well. the ddr2 sdram device will automatically delay the internal precharge command until t ras (min) has been satis? ed. 24. operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 25. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond .
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 26. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are measured from t aofd . 27. this parameter has a two clock minimum requirement at any t ck . 28. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. 29. t isxr is equal to t is and is used for cke setup time during self refresh exit. 30. no more than 4 bank active commands may be issued in a given t faw (min) period. t rrrd (min) restriction still applies. the t faw (min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks already open or closed. 31. t rpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. t rpa (min) applies to all 8-bank ddr2 devices. 32. value is minimum pulse width, not the number of clock registrations. 33. applicable to read cycles only. write cycles generally require additional time due to write recovery time (t wr ) during arto precharge. 34. t cke (min) of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2* t ck + t ih . 35. this parameter is not referenced to a speci? c voltage level, but speci? ed when the device output is no longer driving (t rpst ) or beginning to drive (t rpre ). 36. when dqs is used single-ended, the minimum limit is reduced by 100ps.
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.3 (0.130) 82.127 (3.233) 81.873 (3.223) front view 18.45 (0.726) 18.15 (0.715) 10.0 (0.394) typ 1.0 (0.039) typ 1.00 (0.039) r x2 0.50 (0.02) r 1.80 (0.071) d x2 6.0 (0.236) typ 2.0 (0.079) typ 78.0 (3.071) typ pin 1 pin 122 42.9 (1.689) typ back view typ 3.6 (0.142) typ typ 33.6 (1.323) typ 38.4 (1.512) typ 3.2 (0.126) typ tbd max 1.10 (0.043) 0.90 (0.035) pin 244 pin 123 detail a 3.60 (0.142) full r 3.80 0.10 (0.150 0.004) 1.30 (0.051) 1.00 0.05 (0.039 0.002) 2.55 (0.100) detail b 0.450.03 (0.018 0.001) 0.60 (0.024) 0.25 (0.010) max detail a detail b tolerances: + /- 0.13 (0.005) unless otherwise specified. package dimensions for vlp ad7 * all dimensions are in millimeters and (inches) ordering information for ad7 part number speed/data rate cas latency t rcd t rp height* w3hg264m72eer806ad7xg** 400mhz/800mb/s 6 6 6 18.29mm (0.72") w3hg264m72eer665ad7xg** 333mhz/667mb/s 5 5 5 18.29mm (0.72") w3hg264m72eer534ad7xg 266mhz/533mb/s 4 4 4 18.29mm (0.72") w3hg264m72eer403ad7xg 200mhz/400mb/s 3 3 3 18.29mm (0.72") **contact factory for availability. notes: ? rohs product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide w 3 h g 2 64m 72 e e r xxx ad7 x g wedc memory (sdram) ddr 2 gold dual depth bus width component width (x8) 1.8v registered speed (mb/s) vlp package 244 pin (0.72) component vendor name (m = micron) (s = samsung) g = rohs compliant
w3hg264m72eer-ad7 december 2005 rev. 0 advanced 14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 2x64mx72 ddr2 sdram registered, w/pll, vlp mini-dimm revision history rev # history release date status rev 0 created december 2005 advanced

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